An analog-to-digital (A/D) converter provides a digital output which indicates the magnitude of an unknown analog input signal. Dual slope or integrating type A/D converters typically include an integrator which integrates an unknown analog input voltage over a fixed period of time which is usually referred to as the integrate cycle, T.sub.INT. During a subsequent deintegrate cycle, the integrated signal is deintegrated by a known reference voltage until the deintegrated signal as sensed by a comparator reaches a predetermined level (referred to as zero crossing). The variable duration T.sub.DE of the deintegrate cycle is proportional to the magnitude of the analog input voltage, since the ratio of the input voltage V.sub.IN to the reference voltage V.sub.REF is equal to the ratio of the deintegrate cycle to the integrate cycle (T.sub.INT) according to the well-known equation: EQU T.sub.DE =-V.sub.IN .times.T.sub.INT /V.sub.REF
The duration of the deintegrate cycle can be measured by counting clock pulses, which provides a digital representation of the analog input voltage. The advantage of the dual slope integration technique is that the system becomes insensitive to the values of most of the circuit parameters. The values of the integrating resistor and capacitor of the integrator and the clock period all cancel from the final measurement.
A major drawback of the integrating type A/D converter is its relatively slow speed which is necessitated by the need to obtain a high accuracy time measurement for the zero crossing of the deintegrate cycle. Although the clock speed may be increased, the use of a fast clock is limited by the delay of the comparator in detecting the zero crossing. In order to obtain an accurate count of the deintegration time, the comparator delay should be no more than one-half clock pulse. Using the clock delay pulse criterion, the clock frequency of a typical converter would be limited to 160,000 Hz or approximately 20 readings per second for a 12 bit-conversion.
One solution to the slow speed of the integrating type A/D converter is described in commonly-owned U.S. Pat. No. 4,568,913 to Lee L. Evans entitled HIGH SPEED INTEGRATING ANALOG-TO-DIGITAL CONVERTER issued on Feb. 4, 1986, assigned to Intersil, Inc., which is incorporated herein by reference. This A/D converter measures, in a first deintegrate cycle, a first approximation of the analog input voltage over a very short period, e.g. 128 counts as compared with a typical prior art period of over 8,000 counts. The deintegrate cycle count is stopped at the precise point when a new clock pulse begins after the integrator output crosses zero. The difference between the actual zero crossing point and the measured zero crossing count corresponds to a residual output of the integrator. To obtain a more accurate measurement of the true discharging time, the residual output of the integrator is multiplied by a predetermined scale factor and fed back to the integrator for measurement of the residual error. By subtracting the residual error from the first time measurement, a more accurate measurement of the actual discharge time can be obtained.
The general construction of the A/D converter circuit of the above-mentioned Evans patent is described below with reference to FIG. 1. The converter circuit includes a buffer 30. The buffer 30 receives an unknown analog input signal V.sub.IN from a switched input terminal 20. The output of the buffer 30 is connected through a resistor 34, and the appropriate states of switches 64 and 66, to an integrator 36 which includes an amplifier 36a and integrating capacitor 36b and an auto-zero capacitor 32. The output of the integrator 36 is connected to one input (non-inverting) of a comparator 38, the output of which is connected to the input of a zero crossing detector 48 and a control logic unit 52. The integrator output is also connected to a voltage multiplier 40 which includes a resistor 40a, another resistor 40b which has a value equal to a predetermined scale factor, e.g., eight times the value of resistor 40a, and an amplifier 40c. As is well known, amplifier 40c is a standard operational amplifier employed in a multiplier configuration as above described. The output of the voltage multiplier 40 is selectively connected through switches 68 and 70 to a sample-and-hold capacitor 42.
An initial auto-zero cycle is performed, by closing switches 62, 66, 68, and 72, and opening the remainder of the switches, in order to correct for offset voltages of the active devices. For the first integrate cycle, the control logic unit 52 opens the switches 62 and 72 and selects the upper position of the switched input 20 to allow the input signal V.sub.IN to be fed to the buffer 30. The signal is integrated by the integrator 36 for a predetermined number of clock pulses. The input signal V.sub.IN may have a positive or negative polarity, which is sensed and used to set a polarity bit of the output digital representation. During the deintegrate cycle, the input 20 is switched to a reference voltage V.sub.REF of opposite polarity from the input signal and therefore causes the integrator 36 to deintegrate or discharge towards a predetermined level (zero) at a known rate. The technique of determining the polarity of the unknown input signal, selecting the polarity of the reference voltage, and setting the states of the analog switches of the conversion circuit by control signals from the control logic unit 52 are well known.
On the first clock pulse after the output of the comparator 38 crosses zero, the flip-flop 50 generates a pulse to the control logic 52, which then stops the deintegration by opening switch 66 and closing switch 64 in order to isolate the integrator 36 from the input 20. Switch 64 directs the output of the buffer 36 to ground via resistor 34. At this point, switch 70 is closed and the residual output of the integrator 36, multiplied by the selected scale factor, is stored in the capacitor 42. The control logic 52 then opens switch 68 to decouple the output of the voltage multiplier 40 from the capacitor 42. At the same time, switch 74 is closed and the residual value is fed back to the integrator 36 for the residual error measurement. The residual measurement process may be repeated a further time for greater accuracy in the measurement of the actual deintegration time. The count of the deintegration time is maintained by the counter unit 56, converted to digital bits by the register unit 58, and outputted to the display 60. With this type of circuit, 12-bit measurements can be made in cycles of less than 200 clock pulses.
A/D converters of the type described above have been used in monolithic ADC components. However, several factors have prevented monolithic ADC's from achieving 5-digit or greater accuracy. The high gains required for buffering and amplifying are difficult to obtain with CMOS processes typically used for commercial integrating type ADC's. The system noise is also difficult to control and has been known to cause "flickering" of the least significant digits in some ADC converters.
These shortcomings in conventional monolithic ADC's are being addressed by the emergence of bipolar MOS circuits (BiMOS) as a production process alternative for high-performance analog-digital circuits. As compared to MOS transistors, bipolar transistors allow the fabrication of higher gain amplifiers with higher bandwidths and lower offsets. Bipolar transistors also have considerably lower 1/f noise than comparably sized MOS transistors. The bipolar transistors are therefore used in the input stages of the buffers and integrator to improve noise and gain, while the actual input devices are MOS for minimum input bias current. The advantageous use of monolithic BiMOS ADC's is discussed, for example, in an article entitled "A Monolithic .+-.51/2-Digit BiMOS A/D Converter", by Bertram Rodgers and Charles Thurber, IEEE Journal of Solid-State Circuits, Vol. 24, No. 3, Jun. 1989, pp. 617-626, which is incorporated herein by reference. The Rodgers and Thurber article also discusses a multiple integration algorithm wherein an integrate/deintegrate measurement cycle is divided up into subsections of the analog input signal and includes further measurement cycles for residual error.
As distinct from the fabrication of transistors for high-performance analog-digital circuits, the use of bipolar inputs concerns the application of positive and negative voltage inputs (with respect to a common level or ground) to the differential input of an A/D converter. One problem with digital conversion of bi-polar inputs to the integrating type A/D converter in general is that a difference in reading (disregarding the polarity bit) may be obtained between a positive and negative input of the same magnitude. This problem is due to a difference in the performance of the integrator in the integrate and deintegrate phases. As shown with reference to FIG. 2, the operation of the integrator in different voltage ranges for a positive, e.g., +1.5 volt, input (solid line) as compared with a negative input (dashed line) of the same magnitude, can result in a difference in the magnitudes of the integrator outputs in the integrate phase, and also a different ramp-down zero-crossing point in the deintegrate phase, which are referred to together as "rollover error". The rollover error is attributed to operation of the integrator in opposite ramping-up and ramping-down directions, particularly in the lower voltage ranges. The rollover error leads to a difference E.sub.R in the output pulse counts for the respective discharge times. Also, differences occur in the response of the comparator to positive or negative ramp voltages at its input, and hence the zero-crossing measurements, due to hysteresis in the comparator response.
The present invention provides an improvement in dual slope or integrating type A/D converters which greatly reduces or eliminates rollover error. The structure and circuitry described herein provides an improved A/D converter without rollover error which can be used in monolithic BiMOS circuits. Using the techniques to be described, one is also able to reduce the number of components of the A/D converter which would otherwise add to cost or space requirements.